Semiconductor device and manufacturing method for the same

ABSTRACT

A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip, is significantly larger than the first semiconductor chip in a configuration wherein two semiconductor chips are stacked and mounted on a wiring board. In this semiconductor device the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the side of the adhesive is inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the side of the first semiconductor chip. Therefore, it becomes possible to prevent the occurrence of microcracks in the second semiconductor chip and to prevent the occurrence of defective fine metal wire connections caused by the impact at the time of electrical connection of the second semiconductor chip to the wiring board.

This is a divisional application of application Ser. No. 10/636,595filed Aug. 8, 2003.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device molded in resinwherein a plurality of semiconductor chips and passive parts are mountedwithin one semiconductor device molded in resin and to a manufacturingmethod for the same. The present invention relates, in particular, to asemiconductor device molded in resin wherein two semiconductor chips arestacked and mounted on a wiring board and to a manufacturing method forthe same.

2. Description of the Background Art

In recent years reduction in the weight and thickness of mobileapparatuses, as represented by notebook personal computers, cellularphones, and the like, has rapidly progressed. According to such a trendan increase in the density of electronic parts and an enhancement inperformance are required for electronic parts mounted on the motherboards of the apparatuses, in particular, for semiconductor devices,which make up the core of the apparatuses. Conventionally an MCM(multichip module) wherein a plurality of semiconductor chips is mountedon a plane surface of an interposer (substrate having external terminalsfor direct mounting on a mother board), for example, is generally used(see Japanese unexamined patent publication H09 (1997)-8220 (FIG. 1)) inthe case wherein a plurality of semiconductor chips is incorporatedwithin one semiconductor device. Moreover, in order to further increasethe configuration density within the semiconductor device, a method ofstacking semiconductor chips, for example, has come into wide use (seeJapanese unexamined patent publication H11 (1999)-204720 (FIGS. 1 and3)). The size of a semiconductor chip mounted above the lower chip is,in general, smaller than the lower chip to make connection of fine metalwires easy in the case wherein a plurality of semiconductor chips isstacked in a conventional manner. In some cases, however, the dimensionsof the upper semiconductor chip are greater than that of the lower chipin the configuration wherein the lower chip is, for example, directlybonded to a board and the upper semiconductor chip is mounted on thelower chip so that the electric circuit thereof faces upward (seeJapanese unexamined patent publication 2000-299431 (FIG. 1) and Japaneseunexamined patent publication 2001-320014 (FIG. 1)). These casesdisclose a technique of supporting the upper chip with supports, orsupport members.

The upper semiconductor chip is larger than the lower semiconductor chipand the upper semiconductor chip is in a condition extending in anoverhanging manner over the lower semiconductor chip, which is a flipchip, in a conventional semiconductor device molded in resin having aconfiguration wherein the lower semiconductor chip is directly flip chipbonded to a carrier board and the upper semiconductor chip is mounted onthe lower chip with the electric circuit thereof facing upward. In thiscase microcracks may occur in the upper semiconductor chip or defectiveconnections of fine metal wires may occur due to impact at the time ofconnection of fine metal wires to the upper semiconductor chip by meansof an ultrasonic wave or thermocompression bonding method.

Here, a problem is described in reference to FIGS. 10A and 10B. FIG. 10Ais a cross sectional view showing a conventional semiconductor devicemolded in resin and FIG. 10B shows an enlarged view of a portion of FIG.10A. In addition, the enlarged view shows the phenomenon that is theproblem. In a semiconductor device molded in resin having aconfiguration wherein first semiconductor chip 1, is directly flip chipbonded to a carrier board 20 and a second semiconductor chip 2 ismounted on first semiconductor chip 1 so that the electric circuitthereof faces upward, Au wires 7 are connected to electrode pads 4 ofsecond semiconductor chip 2 using capillary 10, as shown in FIGS. 10Aand 10B. At this time second semiconductor chip 2 bends symbol (11indicates the amount of bending Δh) due to the impact from the load whenball bonding is carried out while ultrasonic waves and the load arebeing applied to an electrode pad 4 at a high temperature (from 150° C.to 250° C.) in the case wherein second semiconductor chip 2 issignificantly larger than first semiconductor chip 1. Therefore, amicroscopic crack 12 occurs in the case wherein an Au wire 7 cannot bestably bonded or in the case wherein the load is too great. Stud bumpsare denoted by symbol 5, conductive paste is denoted by symbol 6,underfill resin is denoted by symbol 13 and adhesive is denoted bysymbol 14 in FIGS. 10A and 10B.

SUMMARY OF THE INVENTION

A purpose of the present invention is to provide a semiconductor deviceand a manufacturing method for the same wherein the reliability ofconnections of fine metal wires connecting an upper semiconductor chipto a wiring board can be improved in the case wherein the uppersemiconductor chip, which is located above a lower semiconductor chip,is significantly larger than the lower semiconductor chip in aconfiguration wherein the two semiconductor chips are stacked andmounted on a wiring board.

In order to achieve the above described purpose, a semiconductor deviceof the first invention is provided with: a wiring board having a firstwiring electrode and a second wiring electrode; a first semiconductorchip having, on the top surface, an electrode connected to the firstwiring electrode; and a second semiconductor chip, which is mounted onthe first semiconductor chip, which is larger than the firstsemiconductor chip and which has, at least in the periphery of the topsurface, an electrode electrically connected to the second wiringelectrode by means of a fine metal wire, wherein the rear surface of thefirst semiconductor chip and the rear surface of the secondsemiconductor chip are adhered to each other by means of adhesive andthe sides of the adhesive are inclined from the edge portions of thefirst semiconductor chip toward the portions of the second semiconductorchip extending from the sides of the first semiconductor chip.

According to this configuration the rear surface of the firstsemiconductor chip and the rear surface of the second semiconductor chipare adhered to each other by means of adhesive and the side of theadhesive is inclined from the edge portions of the first semiconductorchip toward the portions of the second semiconductor chip extending fromthe sides of the first semiconductor chip and, therefore, the size andform of the the adhesive can be optimized. Therefore, it becomespossible to prevent the occurrence of microcracks in the secondsemiconductor chip and to prevent the occurrence of defective fine metalwire connections caused by the impact at the time of electricalconnection of the second semiconductor chip to the wiring board.Thereby, a semiconductor device of a high reliability molded in resinwherein semiconductor chips are stacked can be provided.

A semiconductor device of the second invention is the semiconductordevice of the first invention wherein the area of the cross section ofthe adhesive in a plane along the plane direction of the firstsemiconductor chip is no less than the area of the rear surface of thefirst semiconductor chip. According to this configuration the area ofthe cross section of the adhesive in a plane along the plane directionof the first semiconductor chip is no less than the area of the rearsurface of the first semiconductor chip and, therefore, an adhesivehaving a size that is significantly greater than that of the firstsemiconductor chip and a sufficient thickness can be formed on the rearsurface of the second semiconductor chip. Thereby, defective bondingcaused by the impact to the fine metal wires and microcracks in thesecond semiconductor chip can be further prevented.

A semiconductor device of the third invention is the semiconductordevice of the first invention wherein the surface of the side of theadhesive is in a concave, curved form. According to this configurationthe surface of the side of the adhesive is in a concave, curved formand, therefore, a cross section of the adhesive perpendicular to therear surface of the first semiconductor chip is in an inverted archedform, wherein sufficient stiffness for bearing mechanical stress isprovided in the same manner as in a bridge pier so as to be able to bearthe load from wire bonding.

A semiconductor device of the fourth invention is the semiconductordevice of the first invention wherein the adhesive is formed over theentire region of the rear surface and over a portion of the sides of thefirst semiconductor chip. According to this configuration the adhesiveis formed over the entire region of the rear surface and over a portionof the sides of the first semiconductor chip and, therefore, theapplication of a bending moment force with a starting point at thecorner portion of the rear surface of the first semiconductor chip canbe suppressed in the case wherein the load from wiring bonding isapplied to the electrode of the second semiconductor chip.

A semiconductor device of the fifth invention is the semiconductordevice of the first invention wherein an underfill resin is placedbetween the wiring board and the first semiconductor chip and wherein atleast a portion of the side of the underfill resin is covered with anadhesive. According to this configuration an underfill resin is placedbetween the wiring board and the first semiconductor chip and at least aportion of the side of the underfill resin is covered with an adhesiveand, therefore, the application of a bending moment force with astarting point at the corner portion of the rear surface of the firstsemiconductor chip can be further suppressed.

A semiconductor device of the sixth invention is the semiconductordevice of the first invention wherein a passive part is electricallyconnected to the mounting surface of the first semiconductor chip on thewiring board, wherein the second semiconductor chip is larger than theregion where the first semiconductor chip and the passive part areplaced and wherein the rear surface of the second semiconductor chip andthe rear surface of the passive part facing the rear surface of thesecond semiconductor chip are adhered to each other. According to thisconfiguration a passive part is electrically connected to the mountingsurface of the first semiconductor chip on the wiring board, wherein thesecond semiconductor chip is larger than the region where the firstsemiconductor chip and the passive part are placed and wherein the rearsurface of the second semiconductor chip and the rear surface of thepassive part facing the rear surface of the second semiconductor chipare adhered to each other and, therefore, the same working effects as ofthe first invention can be gained in a semiconductor device wherein aplurality of semiconductor chips and a passive part are mounted.

A semiconductor device of the seventh invention is the semiconductordevice of the first invention wherein a passive part is electricallyconnected to the mounting surface of the first semiconductor chip on thewiring board, wherein the second semiconductor chip is larger than theregion where the first semiconductor chip and the passive part areplaced, wherein a spacer is adhered to the rear surface of the passivepart so that the height of the spacer becomes approximately equal to theheight of the rear surface of the first semiconductor chip and whereinthe rear surface of the second semiconductor chip and the rear surfaceof the passive part facing the rear surface of the second semiconductorchip are adhered to each other in the condition wherein the spacer isintervened therebetween. According to this configuration a spacer isadhered to the rear surface of a passive part so that the height of thespacer becomes approximately equal to the height of the rear surface ofthe first semiconductor chip and, therefore, the second semiconductorchip is maintained in a stable condition even in the case wherein theheight of the rear surface of the first semiconductor chip and theheight of the rear surface of the passive part differ from each otherand the load from wire bonding is applied to the electrode of the secondsemiconductor chip.

A manufacturing method for a semiconductor device of the eighthinvention is provided with: the step of preparing a wiring board havinga first wiring electrode and a second wiring electrode as well as afirst semiconductor chip having an electrode on the top surface; thestep of electrically connecting the first wiring electrode of the wiringboard to the electrode of the first semiconductor chip via a bump; thestep of preparing a second semiconductor chip that is larger than thefirst semiconductor chip and that has an electrode in at least theperiphery of the top surface; the step of adhering the rear surface ofthe first semiconductor chip, which is the side opposite to theelectrode, and the rear surface of the second semiconductor, which isthe side opposite to the electrode, to each other by means of adhesive;and the step of connecting the electrode of the second semiconductorchip to the second wiring electrode of the wiring board by means of afine metal wire, wherein the adhesive is formed so that the side of theadhesive is inclined from the end portions of the first semiconductorchip toward the portions of the second semiconductor chip extending fromthe sides of the first semiconductor chip at the time of the step ofadhering the first semiconductor chip and the second semiconductor chipto each other.

According to this configuration the adhesive is formed to have anoptimized size and form so that the side of the adhesive is inclinedfrom the end portions of the first semiconductor chip toward theportions of the second semiconductor chip extending from the sides ofthe first semiconductor chip at the time of the step of adhering thefirst semiconductor chip and the second semiconductor chip to each otherand, thereby, it becomes possible to prevent the occurrence of defectivebonding caused by the impact to the fine metal wires for electricallyconnecting the second semiconductor chip to the wiring board and toprevent the occurrence of microcracks in the second semiconductor chip.Thereby, a manufacturing method for a semiconductor device of a highreliability molded in resin wherein semiconductor chips are stacked canbe provided.

A manufacturing method for a semiconductor device of the ninth inventionis the manufacturing method for a semiconductor device of the eighthinvention wherein the fine metal wire is connected to the electrode ofthe second semiconductor chip after a molten ball is formed of the endof the fine metal wire on the second wiring electrode of the wiringboard at the time of the step of connecting the second semiconductorchip to the wiring board by means of the fine metal wire. According tothis configuration the fine metal wire is connected to the electrode ofthe second semiconductor chip after a molten ball is formed of the endof the fine metal wire on the second wiring electrode of the wiringboard at the time of the step of connecting the second semiconductorchip to the wiring board by means of the fine metal wire and, therefore,it becomes possible limit the height above the second semiconductor chipof the fine metal wires to a low height.

A manufacturing method for a semiconductor device of the tenth inventionis the manufacturing method for a semiconductor device of the eighthinvention wherein the wiring board and a passive part are electricallyconnected to each other at the time of the step of electricallyconnecting the wiring board to the first semiconductor chip and whereinthe rear surface of the second semiconductor chip and the rear surfaceof the passive part facing the rear surface of the second semiconductorchip are adhered to each other in the case wherein a spacer isintervened therebetween so that the height of the rear surface of thefirst semiconductor chip and the height of the spacer becomeapproximately equal at the time of the step of adhering the firstsemiconductor chip to the second semiconductor chip.

According to this configuration the wiring board and a passive part areelectrically connected to each other at the time of the step ofelectrically connecting the wiring board to the first semiconductor chipand, therefore, the same working effects as of the eighth invention canbe gained in a semiconductor device wherein a plurality of semiconductorchips and a passive part are mounted. In addition, the rear surface ofthe second semiconductor chip and the rear surface of the passive partfacing the rear surface of the second semiconductor chip are adhered toeach other in the case wherein a spacer is intervened therebetween sothat the height of the rear surface of the first semiconductor chip andthe height of the spacer become approximately equal at the time of thestep of adhering the first semiconductor chip to the secondsemiconductor chip and, therefore, the second semiconductor chip can bemaintained in a stable condition at the time of connecting the secondsemiconductor chip to the wiring board by means of fine metal wires evenin the case wherein the height of the rear surface of the firstsemiconductor chip and height of the rear surface of the passive partdiffer from each other.

A manufacturing method for a semiconductor device of the eleventhinvention is the manufacturing method for a semiconductor device of theeighth invention wherein the wiring board and a passive part areelectrically connected to each other and an underfill resin is placedbetween the wiring board and the first semiconductor chip at the time ofthe step of electrically connecting the wiring board to the firstsemiconductor chip and wherein the rear surface of the secondsemiconductor chip and the rear surface of the passive part facing therear surface of the second semiconductor chip are adhered to each otherin the case wherein a spacer is intervened therebetween so that theheight of the rear surface of the first semiconductor chip and theheight of the spacer become approximately equal and a material having athixotropy greater than that of the underfill resin is used for thespacer at the time of the step of adhering the first semiconductor chipto the second semiconductor chip. It is necessary to fill in theunderfill resin by injection into a narrow gap (from several μm toseveral tens of μm) between the first semiconductor chip and the wiringboard and, therefore, a low thixotropy is required for the underfillresin while it is necessary for the spacer to be transformed in aplastic manner so that the surface of the spacer and the rear surface ofthe first semiconductor chip share approximately the same plane in thecase wherein an arbitrary load is applied at the time when the secondsemiconductor chip is mounted and, therefore, it is important for thethixotropic ratio of the spacer to be greater than that of the underfillresin so that the spacer plays a most important role.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a perspective view showing semiconductor chips utilized in asemiconductor device molded in resin according to one embodiment of thepresent invention and FIG. 1B is a cross sectional view thereof;

FIG. 2A is a plan view showing a first semiconductor chip utilized in asemiconductor device molded in resin according to one embodiment of thepresent invention, FIG. 2B is an enlarged view of a main portion of thefirst semiconductor chip and FIG. 2C is a view for describing theformation of an electrode pad;

FIG. 3 is a plan view showing a sheet board utilized in a semiconductordevice molded in resin according to one embodiment of the presentinvention;

FIG. 4A is a plan view of the surface of the carrier board on whichsemiconductor elements are mounted in FIG. 3, FIG. 4B is a crosssectional view along line a-a′ and FIG. 4C is a plan view of theexternal terminal side of the carrier board;

FIGS. 5A to 5D are cross sectional views showing a semiconductor devicemolded in resin during manufacturing steps according to one embodimentof the present invention;

FIGS. 6A and 6B are cross sectional views during the steps following thesteps of FIGS. 5A to 5D;

FIG. 7 is a cross sectional view showing the form of an adhesiveaccording to one embodiment of the present invention;

FIGS. 8A to 8C are cross sectional views of a semiconductor devicemolded in resin according to another embodiment of the presentinvention;

FIG. 9A is a partially penetrative plan view of a semiconductor devicemolded in resin according to still another embodiment of the presentinvention and FIG. 9B is a cross sectional view thereof; and

FIG. 10A is a cross sectional view showing a semiconductor device moldedin resin according to a prior art and FIG. 10B is an enlarged viewshowing a portion thereof.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiments of the present invention are described below withreference to FIGS. 1 to 7. FIG. 1A is a perspective view showingsemiconductor chips utilized in a semiconductor device molded in resinaccording to one embodiment of the present invention and FIG. 1B is across sectional view thereof. Here, a partial cross section of theconfiguration of the semiconductor device is exposed in the perspectiveview for the purpose of ease of understanding.

The semiconductor device molded in resin shown in FIG. 1 is providedwith:

a carrier board (wiring board) 20 having, on the top surface, aplurality of electrodes 22 and 23 as well as board wires 21 connected toelectrodes 22 and 23 and having, on the rear surface, external terminals24 electrically connected to electrodes 22, 23 and board wires 21;

a first semiconductor chip 1 having, on the top surface, electrode pads3 connected to the plurality of electrodes (first wiring electrodes) 22on the top surface of carrier board 20 via conductive paste 6 by meansof Au bumps 5;

an underfill resin 13 that fills in the gap between first semiconductorchip 1 and carrier board 20 and that covers the peripheral edge portionof first semiconductor chip 1;

a second semiconductor chip 2, which is larger than first semiconductorchip 1, has electrode pads 4 in at least the periphery of the topsurface and is connected to first semiconductor chip 1 back-to-back bymeans of an adhesive 14 having a thickness;

Au wires 7 for connecting electrode pads 4 of second semiconductor chip2 to electrodes (second wiring electrodes) 23 of carrier board 20; and

a mold resin 25 for covering and sealing first and second semiconductorchips 1 and 2 as well as Au wires 7. In addition, the side of adhesive14 is inclined from the end portions of first semiconductor chip 1toward the portions of second semiconductor chip 2 extending from thesides of the first semiconductor chip.

An alumina-based ceramic board, an aluminum nitride-based ceramic board,or the like, is used for carrier board 20. In addition, an insulatingsingle layer, or multilayer, circuit board, or the like, made of anorganic board, such as an epoxy board, may be used as another material.In addition, when a plurality of electrodes 22 on the top surface ofcarrier board 20 and electrode pads 3 on first semiconductor chip 1 areconnected, conductive paste 6, such as Ag—Pd paste, is supplied to Aubumps 5 and first semiconductor chip 1, of which the top surface facesdownward, is mounted onto carrier board 20 and conductive paste 6 ishardened. Thereby, the electrical and mechanical connections betweencarrier board 20 and first semiconductor chip 1 are secured. Inaddition, liquid molding resin is utilized as underfill resin 13 and,thereby, the gap between carrier substrate 20 and first semiconductorchip 1 is filled in and the peripheral end portions of firstsemiconductor chip 1 are covered. Adhesive 14, having a thickness, thatconnects first semiconductor chip 1 and second semiconductor chip 2back-to-back may be adhesive layers applied to both surfaces of a tapematerial or may be an adhesive in a jelly form, such as a silicon-basedadhesive. An important factor herein is that the thickness of theadhesive be arbitrarily set at a value between several tens of μm toseveral hundreds of μm and that the form of the cross section thereof bein a tapered form (oblique angle) or in an R surface form (concave,curved surface) and it is important for the adhesive to have an areathat is significantly larger than that of first semiconductor chip 1.

FIG. 2A is a plan view showing a first semiconductor chip utilized in asemiconductor device molded in resin according to one embodiment of thepresent invention, FIG. 2B is an enlarged view of a main portion of thefirst semiconductor chip and FIG. 2C is a view for describing theformation of an electrode pad.

The wire width according to the wiring rule for integrated circuits insemiconductor chips is, at present, progressing from 0.18 μm to 0.13 μmand, furthermore, to 0.10 μm in order to scale down the microscopicprocess. The pitch of the electrode pads for connection to the outsidehas been reduced in correspondence with the above and the pitch for thealignment of the electrode pads has been scaled down to 100 μm and to 80μm in order to prevent increase in the area of the semiconductor chip.An electrode pad pitch of 60 μm, or less, however, provides a distancebetween adjacent electrode pads that is too narrow for a probeinspection or for the step of flip chip connection after the applicationof conductive paste to Au bumps and, therefore, a method is used whereinelectrode pads 3 are arranged in a zigzag manner, as shown in FIGS. 2Aand 2B. On the other hand, a POE (pad on element) wherein an electrodepad is formed on a circuit element or on a wire of an internal circuitis also generally used in order to prevent increase in the area of asemiconductor integrated circuit.

An Au bump 5 (also referred to as a stud bump, which is a bump in atwo-stage protruding form) is formed on an electrode pad 3 of firstsemiconductor chip 1 using a wire bonding method (ball bonding method)as shown in FIG. 2C. According to this method a ball formed at the endof an Au wire is thermally compressed to an electrode pad 3 having asurface of Al, and thereby, the lower stage of the two-stage protrusionis formed and, furthermore, an Au wire loop is formed by shiftingcapillary 10 so that the upper stage of the two-stage protrusion isformed. The heights of the two-stage protrusions are not uniform and thetops thereof lack flatness in the above described condition and,therefore, leveling is carried out in order to make the heights of thetwo-stage protrusions uniform by compression and in order to make thetops thereof flat. This bump formation method is referred to as studbump formation. Next, conductive paste 6 containing Ag—Pd as conductivematerial is applied to a rotating disk so as to gain an appropriatethickness using a doctor blade method. At this time conductive paste 6is supplied to Au bumps 5 according to a method wherein firstsemiconductor chip 1, on which Au bumps 5 are provided, is pulled upafter being pressed against conductive paste 6, which is a so-calledtransfer method. Conductive paste 6 made of epoxy resin, which is abinder, and of Ag—Pd coprecipitating powder, which is a conductivefiller, for example, is used while taking the reliability and thethermal stress of conductive paste 6 into consideration.

FIG. 3 is a plan view showing a sheet board utilized in a semiconductordevice molded in resin according to one embodiment of the presentinvention, FIG. 4A is a plan view of the surface of the carrier board onwhich semiconductor elements are mounted in FIG. 3, FIG. 4B is a crosssectional view along line a-a′ and FIG. 4C is a plan view of theexternal terminal side of the carrier board.

As shown in FIGS. 3 and 4, carrier board 20 is placed on a plurality ofsheet boards 19. Electrodes 22 and 23 electrically connected to firstand second semiconductor chips are provided on the side of carrier board20 that is connected to the semiconductor chips. In addition, externalterminals 24 are arranged in a grid form on the opposite side. Analumina-based ceramic board, an aluminum nitride-based, or the like, isused for carrier board 20 and the board is formed of a plurality, fromfour to eight, of layers corresponding to the wire density. The wires 21in the respective layers are made of tungsten and the vias connectingthe respective layers are made of molybdenum, which is electricallycondition. In addition, tungsten wires having a thickness of from 10 μmto 30 μm are plated by means of non-electrode plating with Ni having athickness of several μms and, in addition, they are plated with an Aulayer having a thickness of from approximately 0.1 μm to 0.8 μm in orderto form electrodes 22 and 23, which are electrically connected to thefirst and second semiconductor chips, and terminals 24 on the surface ofthe ceramic board. The thickness of the board is from 0.40 mm to 0.60mm. Broken lines surrounding carrier boards 20, arranged on sheet boards19, indicate molding lines 26 of resin molds integrally sealing aplurality of carrier boards 20. One-dotted chained lines between carrierboards 20 indicate the dividing lines 28 between products for divisioninto individual semiconductor devices molded in resin.

Next, a manufacturing method for a semiconductor device is described.FIGS. 5A to 5D and FIGS. 6A and 6B are cross sectional views showing asemiconductor device molded in resin during a manufacturing processaccording to one embodiment of the present invention.

FIG. 5A shows the step of connecting first semiconductor chip 1, whichis a flip chip, to carrier board 20. According to a flip chip systemwherein the top surface of first semiconductor chip 1 is made to facedownward for mounting, Au bumps 5 on first semiconductor chip 1, towhich conductive paste 6 is supplied, and electrodes 22 on carrier board20, on the bottom surface of which external terminals 24 are formed atconstant intervals in a grid form, are positioned with a high precisionso as to be connected to each other and, after that, thermosetting iscarried out at a constant temperature. This connection method isreferred to as the SBB (stud bump bonding) method. Here, the formationof Au bumps 5 and conductive paste 6 are described in detail above inreference to FIG. 2 and a description thereof is omitted here.

Next, FIG. 5B shows the step of sealing the gap beneath firstsemiconductor chip 1, which has been connected as a flip chip, withunderfill resin 13. This is the step wherein molding with resin iscarried out by injecting underfill resin 13, which is a liquid epoxyresin that is a thermosetting resin, into the gap created between firstsemiconductor chip 1 and carrier board 20 as well as into the peripheralportion around first semiconductor chip 1 by means of nozzle 29 and ofhardening the resin. The purpose of this step is to protect theintegrated circuit on the top surface of first semiconductor chip 1 aswell as Au bumps 5 and conductive paste 6 over electrode pads 3.

Next, FIG. 5C shows the step of adhering the rear surface of firstsemiconductor chip 1 to the rear surface of second semiconductor chip 2back-to-back. Adhesive 14 having a size that is significantly largerthan first semiconductor chip 1 and having a thickness is temporarilyadhered to the rear surface of second semiconductor chip 2. Adhesive 14may be formed of adhesive layers that have been applied to both sides ofa tape material in advance or may be an adhesive in a jelly form, suchas a silicon-based adhesive. An important factor herein is that thethickness of adhesive 14 be arbitrarily set at a value between severaltens of μm to several hundreds of μm and that the form of the crosssection of the side of adhesive 14 be in a tapered form (oblique angle)or in an R surface form (curved surface). Adhesive 14, having a sizegreater than that of first semiconductor chip 1, is prepared and isattached to the rear surface of second semiconductor chip 2 by means ofa tool. At this time a tape having excellent releasability may beattached to the tool in order to prevent adhesive 14 from becoming stuckto the tool.

Though not shown, a concrete adhesive method is described wherein adicing sheet is attached to the top surface of second semiconductorchips 2, which are still in a wafer, and dicing is carried out from therear surface of second semiconductor chips 2. After that, secondsemiconductor chips 2 that are good products are selected according tothe above conditions and, then, adhesive 14 is attached to the rearsurfaces of these chips. Next, these chips are adhered and fixed to therear surfaces of first semiconductor chips 1 via the dicing sheet.

Next, FIG. 5D shows the step of electrically connecting secondsemiconductor chip 2 to carrier board 20 by means of Au wires 7. Anultrasonic wave and thermal compression method is used as a method forelectrically connecting second semiconductor chip 2 to carrier board 20by means of Au wires 7. The end of Au wire 7 is made molten by means ofa spark and is formed into a ball under the condition wherein Au wire 7has been threaded through capillary 10. Ultrasonic wave compression iscarried out on the formed ball that is pressed to electrode 23 usingcapillary 10 so as to form a 1st side (ball side) 8. At this timecarrier board 20 including second semiconductor chip 2 is heated to from150° C. to 250° C. Next, loop control is carried out on Au wire 7 bymeans of capillary 10 and the wire is connected to electrode pad 4 onsecond semiconductor chip 2 so as to form a 2nd side (crescent side) 9.

According to the embodiment of the present invention a so-called reversewire bonding method is used wherein the order of formation of the 1stside and 2nd side, which is the order of connection of the wires, isopposite to that of the generally and widely used wire bonding method.The merit of this method is that it is possible to limit the heightabove the second semiconductor chip 2 of Au wires 7 to a low height.Though not shown, there is a method for connecting the 2nd side of Auwire 7 to an Au bump by forming the Au bump on an electrode pad 4 inadvance. A method wherein the step of covering the surface of electrodepads with Al, for example, is omitted so that Cu in the lower layer isexposed and Au bumps are formed directly on Cu and, then, the 2nd sideof Au wire 7 is connected to an Au bump is cost effective. Here, Au wire7 is made of gold (Au) with a purity of 99.99%, or higher, and has adiameter ranging from 15 μm to 30 μm while electrode pads have a surfaceof Al.

FIG. 6A shows a cross sectional view of a semiconductor device molded inresin. A semiconductor device, which is a semi-finished product, thathas been completed through the steps up to and including the steps inFIG. 5D is placed in a resin molding die set (not shown) and issandwiched therebetween. A thermosetting epoxy resin is heated to atemperature of from 150° C. to 200° C. so as to be liquefied and aportion of the product covering the outside of a semiconductor device isformed as a resin mold. After that the resin is hardened within themolding die set for a period of time of hardening of several tens ofseconds and the product is removed from the die set. The molding resinside of a semiconductor device is fixed to an adhesive tape or is fixedby means of vacuum suction, for example, and the mold is divided intoindividual products along dividing lines 28 between products using adicer with a blade or a laser as a cutting means for product division.

FIG. 6B shows a cross sectional view of a finished semiconductor devicemolded in resin.

FIG. 7 is an illustration for describing in detail the cross sectionalform of FIG. 1. In cross sectional form 15 of the edge portion ofadhesive 14, located between second semiconductor chip 2 and firstsemiconductor chip 1, the point of contact with second semiconductorchip 2 is located outside the point of contact with first semiconductorchip 1, as shown in FIG. 7. One method for implementing this shape isdescribed above in reference to FIG. 5C. That is to say, at the time ofthe process of adhering first semiconductor chip 1 and secondsemiconductor chip 2 to each other, adhesive 14 is formed so that theside thereof is inclined from the edge portions of first semiconductorchip 1 toward the portions of second semiconductor chip 2, extendingfrom the sides of first semiconductor chip 1. This form has aconfiguration in an inverted arch form, such as in a bridge pier, so asto be able to bear the load from wire bonding.

FIGS. 8A to 8C are cross sectional views of a semiconductor devicemolded in resin according to another embodiment of the presentinvention.

FIG. 8A shows the form of adhesive 14, of which the end portionpartially covers the side of first semiconductor chip 1. This is inorder to gain the same effects as described in reference to FIG. 7 and,in addition, in order to suppress the application of a bending momentforce with a starting point at the corner portion of the rear surface offirst semiconductor chip 1 in the case wherein the load from wiringbonding is applied to electrode pad 4 of second semiconductor chip 2.

FIG. 8B shows a structure wherein the corner portions of the rearsurface of first semiconductor chip 1 are rounded in order to furthersuppress the application of a bending moment force to secondsemiconductor chip 2 with a starting point at the corner portion of therear surface of first semiconductor chip 1 and, in addition, the sameeffects as in FIGS. 7 and 8A are gained.

FIG. 8C shows a structure wherein the edge portion of adhesive 14 coversthe side of first semiconductor chip 1 and makes contact with underfillresin 13 that exists on the side of first semiconductor chip 1.Furthermore, the corner portions of the rear surface of firstsemiconductor chip 1 are rounded so as to form rounded portions 30 andthe application of a bending moment force to second semiconductor chip 2with a starting point at the corner portion of the rear surface of firstsemiconductor chip 1 can be prevented.

FIG. 9A is a partially penetrative plan view of a semiconductor devicemolded in resin according to still another embodiment of the presentinvention and FIG. 9B is a cross sectional view thereof.

As shown in FIGS. 9A and 9B, passive parts 17 are electrically connectedto the mounting surface of first semiconductor chip 1 on carrier board20 and second semiconductor chip 2 is larger than the region whereinfirst semiconductor chip 1 and passive parts 17 are arranged so that therear surface of second semiconductor chip 2 and the rear surfaces ofpassive parts 17 facing the rear surface of second semiconductor chip 2are adhered to each other. In addition, a spacer 16 is adhered to therear surfaces of passive parts 17 so that the height of the spacerbecomes approximately the same as the height of the rear surface offirst semiconductor chip 1. Passive parts 17 are soldered to electrodeson carrier board 20.

The manufacturing process for this semiconductor device is the same asthat shown in FIGS. 5A to 5D and FIGS. 6A and 6B except wherein passiveparts 17 are electrically connected to carrier board 20 in the step(FIG. 5A) of electrically connecting first semiconductor chip 1 tocarrier board 20. The step (FIG. 5C) of adhering first semiconductorchip 1 and second semiconductor chip 2 to each other is carried outunder the condition wherein spacer 16 is intervened between the rearsurface of second semiconductor chip 2 and the rear surfaces of passiveparts 17 facing the rear surface of second semiconductor chip 2 afterthe provision of underfill resin 13 between carrier board 20 and firstsemiconductor chip 1, wherein the height of spacer 16 is approximatelythe same as that of the rear surface of first semiconductor chip 1. Amaterial having a thixotropy greater than that of said underfill resin13 is used for spacer 16.

1-7. (canceled)
 8. A manufacturing method for a semiconductor device,comprising: the step of preparing a wiring board having a first wiringelectrode and a second wiring electrode as well as a first semiconductorchip having an electrode on the top surface; the step of electricallyconnecting the first wiring electrode of said wiring board to theelectrode of said first semiconductor chip via a bump; the step ofpreparing a second semiconductor chip that is larger than the firstsemiconductor chip and that has an electrode in at least the peripheryof the top surface; the step of adhering the rear surface of said firstsemiconductor chip, which is the side opposite to the electrode, and therear surface of said second semiconductor, which is the side opposite tothe electrode, to each other by means of adhesive; and the step ofconnecting the electrode of said second semiconductor chip to the secondwiring electrode of said wiring board by means of a fine metal wire,wherein said adhesive is formed so that the side of said adhesive isinclined from the end portions of said first semiconductor chip towardthe portions of said second semiconductor chip extending from the sidesof the first semiconductor chip at the time of the step of adhering saidfirst semiconductor chip and said second semiconductor chip to eachother.
 9. The manufacturing method for a semiconductor device accordingto claim 8, wherein said fine metal wire is connected to the electrodeof said second semiconductor chip after a molten ball is formed of theend of said fine metal wire on the second wiring electrode of saidwiring board at the time of the step of connecting the secondsemiconductor chip to the wiring board by means of the fine metal wire.10. The manufacturing method for a semiconductor device according toclaim 8, wherein said wiring board and a passive part are electricallyconnected to each other at the time of the step of electricallyconnecting the wiring board to the first semiconductor chip and whereinthe rear surface of said second semiconductor chip and the rear surfaceof said passive part facing the rear surface of said secondsemiconductor chip are adhered to each other in the case wherein aspacer is intervened therebetween so that the height of the rear surfaceof said first semiconductor chip and the height of the spacer becomeapproximately equal at the time of the step of adhering said firstsemiconductor chip to the second semiconductor chip.
 11. Themanufacturing method for a semiconductor device according to claim 8,wherein said wiring board and a passive part are electrically connectedto each other and an underfill resin is placed between said wiring boardand said first semiconductor chip at the time of the step ofelectrically connecting the wiring board to the first semiconductor chipand wherein the rear surface of said second semiconductor chip and therear surface of said passive part facing the rear surface of said secondsemiconductor chip are adhered to each other in the case wherein aspacer is intervened therebetween so that the height of the rear surfaceof said first semiconductor chip and the height of the spacer becomeapproximately equal and a material having a thixotropy greater than thatof said underfill resin is used for said spacer at the time of the stepof adhering said first semiconductor chip to the second semiconductorchip.